TL;DR
A developer has successfully ported the Project Oberon system to run on RISC-V hardware, replacing its original RISC-5 architecture. This development showcases potential for open-source OS portability and hardware flexibility.
A developer has publicly demonstrated a version of the Project Oberon operating system running on RISC-V hardware, replacing the original RISC-5 architecture. This port signifies a notable step in the system’s adaptability and open-source hardware experimentation, attracting interest from the OS and hardware communities.
The port was shared on the Show HN platform by an individual developer, who provided a working version of Oberon on RISC-V. The original Oberon system, developed by Niklaus Wirth and colleagues, was designed for the RISC-5 architecture, a proprietary processor from the 1980s. The new implementation demonstrates that the system can be adapted to modern, open-source hardware architectures like RISC-V.
According to the developer, the port involved significant modifications to the system’s low-level code, including adapting the boot process, memory management, and device drivers to RISC-V specifications. The project aims to serve as a proof of concept for running legacy academic systems on contemporary, open hardware platforms.
While the port is functional, the developer clarified that it is still a work-in-progress, with some hardware features and peripherals not yet fully supported. The demonstration was accompanied by a video showing the system booting and running basic operations on RISC-V hardware, specifically on a SiFive-based development board.
Potential Impact of Porting Oberon to RISC-V
This development is significant because it shows that a historically influential, minimalist operating system like Oberon can be ported to modern, open-source hardware architectures such as RISC-V. It highlights the flexibility of Oberon’s design and opens possibilities for educational use, research, and hobbyist experimentation with legacy systems on current hardware. Additionally, it underscores the broader trend of adapting academic and experimental OSes to open hardware platforms, fostering innovation and hardware independence.
2Pcs Type-C USB CH32V003 Development Board Minimum System core Board for Nano RISC-V
- Development Board for Nano RISC-V: CH32V003F4U6 chip included
- On-board 24MHz Crystal Oscillator: Ensures stable clock signal
- Powered via Type-C USB: Easy and versatile power source
As an affiliate, we earn on qualifying purchases.
As an affiliate, we earn on qualifying purchases.
Historical and Technical Background of Oberon and RISC-V
Project Oberon was developed in the 1980s at ETH Zurich as both an operating system and a programming environment, emphasizing simplicity and efficiency. Originally designed for the RISC-5 architecture, it was influential in academic circles but remained largely confined to specialized hardware and research settings.
RISC-V, an open-source instruction set architecture, was introduced in the mid-2010s and has gained widespread adoption for its flexibility and openness. It is now used in a variety of devices, from embedded systems to high-performance computing. Porting legacy systems like Oberon to RISC-V aligns with ongoing efforts to modernize and democratize computing platforms.
Prior to this demonstration, there have been other efforts to run Oberon on emulators and different hardware, but a direct port to RISC-V hardware marks a notable milestone in system portability and open-source hardware compatibility.
“This port demonstrates that Oberon can run on modern open hardware, paving the way for further experimentation and educational use.”
— Developer (via Show HN post)
RISC-V FOR EMBEDDED SYSTEMS: THE COMPLETE DEVELOPMENT GUIDE: Build IoT, Automotive, Edge Devices with Open-Source Processors. Microcontrollers, Real-Time OS, AI Acceleration and Production Deployment
As an affiliate, we earn on qualifying purchases.
As an affiliate, we earn on qualifying purchases.
Extent of Hardware Support and Future Development
It is still unclear how fully the port supports all hardware features, peripherals, and performance optimizations on RISC-V. The developer noted that some components, such as certain device drivers, are not yet complete, and stability over extended use remains untested. The long-term maintainability and potential for widespread adoption are still uncertain at this stage.
Wuden CH32V307V-EVT-R1 CH32V307 Evaluation Board RISC-V MCU Onboard Wch-Link WCH RISC-V Development Board 8 UART Ports
- Microcontroller: WCH CH32V307VCT6 32-bit RISC-V @ 144 MHz
- Networking: 10 Mbps Ethernet port
- USB Ports: Two USB 2.0 Type-C ports
As an affiliate, we earn on qualifying purchases.
As an affiliate, we earn on qualifying purchases.
Next Steps for Porting and Community Involvement
The developer plans to continue refining the port, adding support for additional peripherals and improving system stability. They also intend to release the source code publicly, inviting community contributions. Future milestones include enabling full hardware support, benchmarking performance, and exploring use cases in education and research settings.
Premier P550 RISC-V Development Board – Quad-Core SiFive P550 CPU, 16GB/32GB LPDDR5, 128GB eMMC, Ubuntu 24.04 Preinstalled, AI & Linux Development Platform (32GB)
- Processor: Quad-core SiFive P550 CPU up to 1.8GHz
- AI Acceleration: 19.95 TOPS NPU for AI tasks
- Memory Options: 16GB or 32GB LPDDR5 RAM
As an affiliate, we earn on qualifying purchases.
As an affiliate, we earn on qualifying purchases.
Key Questions
What is Project Oberon?
Project Oberon is an operating system and programming environment developed in the 1980s at ETH Zurich, known for its simplicity and efficiency, originally designed for the RISC-5 architecture.
Why is porting Oberon to RISC-V significant?
This demonstrates that legacy academic systems can be adapted to modern, open-source hardware architectures, broadening their usability and educational value.
Will this port be available for public use?
The developer plans to release the source code publicly, but it is still in early stages, with ongoing development and testing.
What hardware was used for the demonstration?
The demonstration was performed on a SiFive-based development board, a common RISC-V platform.
What are the challenges in porting Oberon to RISC-V?
The main challenges include adapting low-level system code, device drivers, and ensuring hardware compatibility and stability.
Source: hn
